In “Bit-Reliability Mapping in LDPC-Codes Modulation systems,” Yan Li and William Ryan, IEEE Communications Letters, vol. 9, no. 1, January 2005, the authors studied the performance of LDPC-coded modulation systems with 8PSK. With the proposed bit reliability mapping strategy, about 0.15 dB performance improvement over a non-interleaving scheme is achieved. The authors also explain the reason for this improvement using an analysis tool called EXIT charts. In the interleaving approach, one interleaving approach is considered and has been shown to offer a better performance over non-interleaving systems, i.e., in the bit-reliability mapping scheme less reliable LDPC codes bits are mapped to the lower level modulation bits and the more reliable bits are mapped to the higher level bits.
Forward error control (FEC) coding is critical for communications systems to ensure reliable transmission of data across noisy communication channels. Based on Shannon's theory, these communication channels exhibit fixed capacity that can be expressed in terms of bits per symbol at certain signal to noise ratio (SNR), which is defined as the Shannon limit. One of the most important research areas in communication and coding theory is to devise coding schemes offering performance approaching the Shannon limit with reasonable complexity. It has been shown that LDPC codes with belief propagation (BP) decoding provide performance close to the Shannon limit with tractable encoding and decoding complexity.
LDPC codes were first described by Gallager in the 1960s. LDPC codes perform remarkably close to the Shannon limit. A binary (N, K) LDPC code, with a code length N and dimension K, is defined by a parity check matrix H of (N-K) rows and N columns. Most entries of the matrix H are zeros and only a small number the entries are ones, hence the matrix H is sparse. Each row of the matrix H represents a check sum, and each column represents a variable, e.g., a bit or symbol. The LDPC codes described by Gallager are regular, i.e., the parity check matrix H has constant-weight rows and columns.
Regular LDPC codes can be extended to irregular LDPC codes, in which the weight of rows and columns vary. An irregular LDPC code is specified by degree distribution polynomials v(x) and c(x), which define the variable and check node degree distributions, respectively. More specifically, let
            v      ⁡              (        x        )              =                  ∑                  j          =          1                          d                      v            ⁢                                                  ⁢            max                              ⁢                        v          j                ⁢                  x                      j            -            1                                and            c      ⁡              (        x        )              =                  ∑                  j          =          1                          d                      c            ⁢                                                  ⁢            max                              ⁢                        c          j                ⁢                  x                      j            -            1                              where the variables dv max and dc max are a maximum variable node degree and a check node degree, respectively, and vj (cj) represents the fraction of edges emanating from variable (check) nodes of degree j.
While irregular LDPC codes can be more complicated to represent and/or implement, it has been shown, both theoretically and empirically, that irregular LDPC codes with properly selected degree distributions outperform regular LDPC codes. FIG. 1 illustrates a parity check matrix representation of an exemplary irregular LDPC code of codeword length six.
LDPC codes can also be represented by bipartite graphs, or Tanner graphs. In Tanner graph, one set of nodes called variable nodes (or bit nodes) corresponds to the bits of the codeword and the other set of nodes called constraints nodes (or check nodes) corresponds the set of parity check constrains which define the LDPC code. Bit nodes and check nodes are connected by edges. A bit node and a check node is said to be neighbors or adjacent if they are connected by an edge. Generally, it is assumed that a pair of nodes is connected by at most one edge.
FIG. 2 illustrates a bipartite graph representation of the irregular LDPC code illustrated in FIG. 1 The LDPC code represented by FIG. 1 is of codeword length 6 and has 4 parity checks. As shown in FIG. 1, there are a total of 9 one's in the parity check matrix representation of the LDPC code. Therefore in the Tanner graph representation shown in FIG. 2, 6 bit nodes 201 are connected to 4 check nodes 202 by 9 edges 203.
LDPC codes can be decoded in various ways, such as majority-logic decoding and iterative decoding. Due to the structures of their parity check matrices, LDPC codes are majority-logic decodable. Although majority-logic decoding requires the least complexity and achieves reasonably good error performance for decoding, some types of LDPC codes with relatively high column weights in their parity check matrices (e.g., Euclidean geometry LDPC and projective geometry LDPC codes), whereas iterative decoding methods have received more attentions due to their better performance versus complexity tradeoffs. Unlike majority-logic decoding, iterative decoding processes the received symbols recursively to improve the reliability of each symbol based on constraints that specify the code. In the first iteration, the iterative decoder only uses the channel output as input, and generates reliability output for each symbol. Subsequently, the output reliability measures of the decoded symbols at the end of each decoding iteration are used as inputs for the next iteration. The decoding process continues until a certain stopping condition is satisfied. Then final decisions are made, based on the output reliability measures of the decoded symbols from the last iteration. According to the different properties of reliability measures used at each iteration, iterative decoding algorithms can be further divided into hard decision, soft decision and hybrid decision algorithms. The corresponding popular algorithms are iterative bit-flipping (BF), belief propagation (BP), and weighted bit-flipping (WBF) decoding, respectively. The BP algorithm has been proven to provide maximum likelihood decoding given the underlying Tanner graph is acyclic. Therefore, it realistically becomes the most popular decoding method. The invention described below, however, only discusses BP decoding of LDPC codes.
BP for LDPC codes is a kind of message passing decoding. Messages transmitted along the edges of the graph are log-likelihood ratio (LLR)
  log  ⁢          ⁢            p      0              p      1      associated with variable nodes corresponding to codeword bits. In this expression p0, and p1 denote the probability that the associated bit takes value 0 and 1, respectively. BP decoding has two steps, horizontal step and vertical step. In the horizontal step, each check node cm sends to each adjacent bit bn a check-to-bit message which is calculated based on all bit-to-check messages incoming to the check cm except the one from bit bn. In the vertical step, each bit node bn sends to each adjacent check node cm a bit-to-check message which is calculated based on all check-to-bit messages incoming to the bit bn except the one from check node cm. These two steps are repeated until a valid codeword is found or the maximum number of iterations is reached.
Because of its remarkable performance with BP decoding, irregular LDPC codes are among the best for many applications. Various irregular LDPC codes have been accepted or being considered for various communication and storage standards, such as DVB-S2/DAB, wireline ADSL, IEEE 802.11n, and IEEE 802.16[4][5]. While considering applying irregular LDPC codes to video broadcasting systems, one often encounter a trouble called error floor.
The error floor performance region of an LDPC decoder can be described by the error performance curve of the system. The LDPC decoder system typically exhibits sharp decrease in error probability as the quality of the input signal improves. The resulting error performance curves are conventionally called waterfall curve and the corresponding region is called waterfall region. At some point, however, the decrease of error probability with input signal quality increase decreases. The resulting flat error performance curve is called error floor. FIG. 3 illustrates an exemplary FER performance curve containing waterfall region 301 and error floor region 302 of an irregular LDPC code.